Browsing by Author Chen, Hung-Ming

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 21 to 40 of 145 < previous   next >
Issue DateTitleAuthor(s)
2006Design migration from peripheral ASIC design to area-10 flip-chip design by chip I/O planning and legalizationChang, Chia-Yi; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2008Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalizationChang, Chia-Yi; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2011Design Planning with 3D-Via Optimization in Alternative Stacking Integrated CircuitsLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Discrete dopant fluctuated 20nm/15nm-gate planar CMOSYang, Fu-Liang; Hwang, Jiunn-Ren; Chen, Hung-Ming; Shen, Jeng-Jung; Yu, Shao-Ming; Li, Yiming; Tang, Denny D.; 電信工程研究所; Institute of Communications Engineering
1-Sep-2008Effective Decap Insertion in Area-Array SoC Floorplan DesignLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2008An effective decap insertion method considering power supply noise during floorplanningLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2013Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear ProgrammingLiu, Sean Shih-Ying; Lee, Chieh-Jui; Huang, Chuan-Chia; Chen, Hung-Ming; Lin, Chang-Tzu; Lee, Chia-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Efficient Analog Layout Prototyping by Layout Reuse with Routing PreservationChin, Ching-Yu; Pan, Po-Cheng; Chen, Hung-Ming; Chen, Tung-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-May-2011Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Mar-2013Escaped Boundary Pins Routing for High-Speed BoardsChin, Ching-Yu; Kuan, Chung-Yi; Tsai, Tsung-Ying; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Fast Analog Layout Prototyping for Nanometer Design MigrationWeng, Yi-Peng; Chen, Hung-Ming; Chen, Tung-Chieh; Pan, Po-Cheng; Chen, Chien-Hung; Chen, Wei-Zen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesignLee, Ren-Jie; Lai, Ming-Fang; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Aug-2009Fast Flip-Chip Pin-Out Designation Respin for Package-Board CodesignLee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-2015A Fast Prototyping Framework for Analog Layout Migration With Planar PreservationPan, Po-Cheng; Chin, Ching-Yu; Chen, Hung-Ming; Chen, Tung-Chieh; Lee, Chin-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-2014Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green FunctionLiu, Sean Shih-Ying; Luo, Ren-Guo; Aroonsantidecha, Suradeth; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green FunctionAroonsantidecha, Suradeth; Liu, Sean Shih-Ying; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2018Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic BiochipsLu, Guan-Ruei; Kuo, Chun-Hao; Chiang, Kuen-Cheng; Banerjee, Ansuman; Bhattacharya, Bhargab B.; Ho, Tsung-Yi; Chen, Hung-Ming; 資訊工程學系; 電機學院; Department of Computer Science; College of Electrical and Computer Engineering
1-Jan-2018Generation of PUP-Keys on FPGAs by K-means Frequency ClusteringAsha, K. A.; Patyal, Abhishek; Chen, Hung-Ming; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-Nov-2011A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost ReductionLin, Chia-Yi; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC RealizationLiao, Wei-Hsun; Lin, Chang-Tzu; Fang, Sheng-Hsin; Huang, Chien-Chia; Chen, Hung-Ming; Kwai, Ding-Ming; Chou, Yung-Fa; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics